Fusible Link Cell with Dual Bit Storage

摘要

A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

主权项

1. A programmable fusible link circuit in an integrated circuit, comprising:
first, second, and third fusible links connected in parallel with one another; a programming circuit for applying a programming voltage across the parallel connected fusible links, the programming voltage selected, responsive to a digital control word of at least two bits, over a range of voltages including a first programming voltage of the first fusible link, a second programming voltage of the second fusible link, and a third programming voltage of the third fusible link; and a sense circuit for outputting a digital output word of at least two bits corresponding to a resistance of the parallel connected fusible links.