| 摘要 |
An integrated circuit includes multiple blocks of circuitry (4, 6, 8) communicating signals via an interface 10 controlled by a clock signal. A clock mesh (20, 22) is used on at least one side of the interface driven by one or more clock drivers (24, 26) that drive the clock mesh with the clock signal communicated with a further block of circuitry. A plurality of interface storage circuits (flip-flops) (12, 14, 16, 18) are coupled to the clock mesh and receive the clock signal from the clock mesh to control storage therein. The interface storage circuits (54) may be of a form controlled by multiple clock signals, CP0, CP1. A signal value D may be captured into the storage circuit upon a rising edge of a first clock signal CP0 and launched from the storage circuit upon the rising edge of a second clock signal CP1. |
