OPEN CAVITY PACKAGE USING CHIP-EMBEDDING TECHNOLOGY

摘要

A method for fabricating packaged semiconductor devices (100) with an open cavity (110a) in panel format; placing (process 201) on an adhesive carrier tape a panel-sized grid of metallic pieces having a flat pad (230) and symmetrically placed vertical pillars (231); attaching (process 202) semiconductor chips (101) with sensor systems face-down onto the tape; laminating (process 203) and thinning (process 204) low CTE insulating material (234) to fill gaps between chips and grid; turning over (process 205) assembly to remove tape; plasma-cleaning assembly front side, sputtering and patterning (process 206) uniform metal layer across assembly and optionally plating (process 209) metal layer to form rerouting traces and extended contact pads for assembly; laminating (process 212) insulating stiffener across panel; opening (process 213) cavities in stiffener to access the sensor system; and singulating (process 214) packaged devices by cutting metallic pieces.

主权项

1. A method for fabricating packaged semiconductor devices comprising:
providing semiconductor chips, each semiconductor chip having a first height and a first surface including a sensor system, terminals, and sidewalls; providing metallic pieces, having a second height greater than the first height, each metallic piece comprising a flat pad having vertical pillars on the flat pad positioned symmetrically relative to a center of the flat pad a flat pad surface opposite the vertical pillars being solderable; placing the vertical pillars on an adhesive carrier tape to form a grid of metallic pieces, the metallic pieces spaced by openings; placing each semiconductor chip inside each opening, each semiconductor chip having the sensor system and the terminals facing downward and the sidewalls spaced by gaps from a sidewall of an adjacent metallic piece; laminating, using an insulating polymer to fill the gaps between each semiconductor chip and the sidewall of the adjacent metallic piece, and to cover a second surface of the semiconductor chip facing away from the adhesive carrier tape; removing the insulating polymer until the flat pad surfaces are exposed while the second surfaces of each semiconductor chip remain covered by the insulating polymer having a surface coplanar with the pad surfaces; turning over the adhesive carrier tape and removing the adhesive carrier tape; sputtering a seed layer of a first metal adhering to the first surfaces of each semiconductor chips, metallic pieces, and the insulating polymer; depositing, patterning and developing a photoresist film on the seed layer to define windows for a network of redistribution traces connecting the terminals to respective metallic pieces while preserving a portion of the photoresist film extending over an area of the seed layer of the first metal; plating a layer of a second metal onto the seed layer of the first metal in the windows; stripping the photoresist film and removing the first and second seed metals beneath the photoresist film; laminating a layer of insulating stiffener over the grid including the first surfaces of the semiconductor chips; and opening a cavity in the layer of insulating stiffener to expose the sensor system of each semiconductor chip.