POWER-AND-GROUND (PG) NETWORK CHARACTERIZATION AND DISTRIBUTED PG NETWORK CREATION FOR HIERARCHICAL CIRCUIT DESIGNS

摘要

A chip layout can include a top-level portion and a set of blocks. The power-and-ground (PG) network for the chip layout can be specified by a set of chip-level PG constraints that is defined using a PG constraint definition language. The set of chip-level PG constraints can be characterized into new sets of PG constraints that correspond to smaller regions of the chip layout, e.g., a set of top-level PG constraints that corresponds to the top-level portion, and a set of block-level PG constraints for each block in the set of blocks. The new sets of PG constraints can then be provided to one or more instances of a PG compiler that executes on one or more processors to create the PG network for the chip layout.

主权项

1. In an electronic design automation (EDA) software tool in a computer, a method for creating a power-and-ground (PG) network for a chip layout, wherein the chip layout includes a top-level portion and a set of blocks, wherein the PG network for the chip layout is specified by a set of chip-level PG constraints that is defined by a user using a PG constraint definition language, the method comprising:
the EDA software tool in the computer determining a set of top-level PG constraints for creating a top-level PG network for the top-level portion of the chip layout based on the set of chip-level PG constraints, wherein the set of top-level PG constraints is defined using the PG constraint definition language; for each block in the set of blocks, the EDA software tool in the computer determining a set of block-level PG constraints based on the set of chip-level PG constraints, wherein the set of block-level PG constraints is defined using the PG constraint definition language; the EDA software tool in the computer creating a PG network in the top-level portion based on the set of top-level PG constraints; and for each block in the set of blocks, the EDA software tool in the computer creating a PG network in the block based on the set of block-level PG constraints associated with the block.