MULTI-PROCESSOR STARTUP SYSTEM

摘要

A switch includes a PCI bus. A line card processor is coupled to a line card memory system and includes a line card processor port connected to the PCI bus. A management processor is coupled to a management memory system and includes a management processor port connected to the PCI bus and associated with a register. The management processor retrieves an OS image and stores the OS image in the management memory system. The management processor then configures the register with a mapping between the management memory system and the line card memory system. The management processor then provides a write instruction to write the OS image to an address range included in the management memory system, and the management processor port converts the write instruction using the address mapping such that the OS image is written over the PCI bus to the line card memory system.

主权项

1. A multi-processor startup system, comprising:
a Peripheral Component Interconnect (PCI) bus; a secondary processing system that is coupled to a secondary memory system and that includes a secondary processing system port that is connected to the PCI bus; a primary processing system that is coupled to a primary memory system and that includes a primary processing system port that is connected to the PCI bus and that is associated with at least one primary port register, wherein the primary processing system is configured to:
retrieve a secondary processing system operating system (OS) image and store the secondary processing system OS image in the primary memory system;configure the at least one primary port register with an address mapping between the primary memory system and the secondary memory system; andcopy the secondary processing system OS image to the secondary memory system by providing a write instruction to write the secondary processing system OS image to an address range included in the primary memory system, wherein the primary processing system port converts the write instruction using the address mapping such that the secondary processing system OS image is written over the PCI bus to the secondary memory system.