发明名称 MODULATING PROCESSOR CORE OPERATIONS
摘要 Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for reducing processor latency through the use of dedicated cores. In one aspect, a method includes a multi-core processor having n cores, including, selecting k cores of the n cores of the multi-core processor to perform dedicated low-latency operations for the n-core processor, where k is less than n, m cores are unselected, and each core of the multi-core processor has a rated core capacity. The methods operate the selected k cores at less than the rated core capacity such that k cores are collectively underutilized by an underutilized capacity and operate one or more of the m cores at a capacity in excess of the rated core capacity such that the m cores operate at a collective capacity that exceeds a collective capacity of the rated core capacities of the m cores.
申请公布号 WO2017011180(A1) 申请公布日期 2017.01.19
申请号 WO2016US39803 申请日期 2016.06.28
申请人 GOOGLE INC. 发明人 BARROSO, Luiz Andre
分类号 G06F9/50 主分类号 G06F9/50
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