发明名称 REDUCING TEST TIME AND SYSTEM-ON-CHIP (SOC) AREA REDUCTION USING SIMULTANEOUS CLOCK CAPTURE BASED ON VOLTAGE SENSOR INPUT
摘要 A method and apparatus for testing an electronic component is provided. The method begins when a design-for-test (DFT) mode is entered and at least one sensor is enabled. Sensor results are monitored and determine the number of cores or capture domains that may be tested simultaneously. The sensors include a voltage and temperature sensor, and either or both sensors may be enabled during testing. Maximum and minimum voltage levels for each capture domain determine at what value a voltage drop occurs. The number of cores selected minimizes a voltage drop across the electronic component. Maximum and minimum temperatures across the multiple cores of the electronic component determine the number of clocks that may be operated simultaneously during testing. An apparatus includes an electronic device to be tested, test sensors on the electronic device, and an interface to a test fixture.
申请公布号 WO2017011119(A1) 申请公布日期 2017.01.19
申请号 WO2016US37281 申请日期 2016.06.13
申请人 QUALCOMM INCORPORATED 发明人 PAL, Dipti Ranjan;GHOSH, Kumar Kanti
分类号 G01R31/3185;G06F1/28 主分类号 G01R31/3185
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