LOW NOISE AMPLIFIER

摘要

A low noise amplifier includes: first and seventh transistors configured to respectively receive first and second input signals; second, third, and fifth transistors connected to the first transistor; eighth, ninth, and eleventh transistors connected to the seventh transistor; a third resistive element; fourth and tenth transistors respectively connected to the third and ninth transistors; sixth and twelfth transistors respectively connected to second and first output terminals; and first and second resistive elements.

主权项

1. A low noise amplifier which receives first and second input signals and outputs first and second output signals, the low noise amplifier comprising:
a first transistor configured to receive the first input signal at its gate; a second transistor having its gate biased, its source electrically connected to a first potential, and its drain electrically connected to a drain of the first transistor; a third transistor having its gate biased and its source electrically connected to the drain of the first transistor; a fourth transistor having its gate biased, its source electrically connected to a second potential, and its drain electrically connected to a drain of the third transistor; a fifth transistor having its gate electrically connected to the drain of the fourth transistor, its source electrically connected to the second potential, and its drain electrically connected to a source of the first transistor; a sixth transistor having its gate electrically connected to the drain of the fourth transistor, its source electrically connected to the second potential, and its drain electrically connected to a second output terminal configured to output the second output signal; a first resistive element, one terminal of which is electrically connected to the first potential and the other terminal of which is electrically connected to the second output terminal; a seventh transistor configured to receive the second input signal at its gate; an eighth transistor having its gate biased, its source electrically connected to the first potential, and its drain electrically connected to a drain of the seventh transistor; a ninth transistor having its gate biased and its source electrically connected to the drain of the seventh transistor; a tenth transistor having its gate biased, its source electrically connected to the second potential, and its drain electrically connected to a drain of the ninth transistor; an eleventh transistor having its gate electrically connected to the drain of the tenth transistor, its source electrically connected to the second potential, and its drain electrically connected to a source of the seventh transistor; a twelfth transistor having its gate electrically connected to the drain of the tenth transistor, its source electrically connected to the second potential, and its drain electrically connected to a first output terminal configured to output the first output signal; a second resistive element, one terminal of which is electrically connected to the first potential and the other terminal of which is electrically connected to the first output terminal; and a third resistive element electrically connected to the source of the first transistor and the source of the seventh transistor.