| 发明名称 |
ERROR CORRECTION DEVICE, SEMICONDUCTOR STORAGE DEVICE, AND ERROR CORRECTION METHOD |
| 摘要 |
There is provided an error correction device with a simple configuration and a high correction capability. An error correction device which can perform c (c<n) error corrections on n-bit encoded data containing a parity bit includes an assumption data setting circuit for setting a plurality of assumption data, containing c error bits and (n−c) or fewer erasure bits, by assuming data of an erasure bit, and a decoding circuit which calculates a syndrome for each of the assumption data set by the assumption data setting circuit and performs decoding based on a calculation result and the parity bit. |
| 申请公布号 |
US2017017545(A1) |
申请公布日期 |
2017.01.19 |
| 申请号 |
US201615144607 |
申请日期 |
2016.05.02 |
| 申请人 |
RENESAS ELECTRONICS CORPORATION |
发明人 |
TANABE AKIRA |
| 分类号 |
G06F11/10;H03M13/15;G11C29/52 |
主分类号 |
G06F11/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An error correction device which can perform c (c<n) error corrections on n-bit encoded data containing a parity bit, the error correction device comprising:
an assumption data setting circuit for setting a plurality of assumption data by assuming data of an erasure bit in encoded data containing c or fewer error bits and (n−c) or fewer bits which cannot be determined to be 0 or 1, that is, erasure bits; and a decoding circuit which calculates a syndrome for each of the assumption data set by the assumption data setting circuit and performs decoding based on a calculation result and the parity bit. |
| 地址 |
TOKYO JP |
