| 发明名称 |
RANDOM NUMBER GENERATION CIRCUIT AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME |
| 摘要 |
A random number generation circuit may include a memory block. The random number generation circuit may include a fuse block configured to store an address of a failed memory cell from a memory cell array of the memory block, as a repair address, and generate a match signal by comparing the repair address with a normal address inputted from an exterior. The random number generation circuit may include a register configured to output a true random number by latching an address corresponding to activation timing of the match signal among normal addresses. |
| 申请公布号 |
US2017018317(A1) |
申请公布日期 |
2017.01.19 |
| 申请号 |
US201514924818 |
申请日期 |
2015.10.28 |
| 申请人 |
SK hynix Inc. |
发明人 |
KIM Kyung Hoon;YOON In Sik |
| 分类号 |
G11C29/00;H04L9/08;G06F7/58;G11C17/16 |
主分类号 |
G11C29/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A random number generation circuit comprising:
a memory block; a fuse block configured to store an address of a failed memory cell from a memory cell array of the memory block, as a repair address, and generate a match signal by comparing the repair address with a normal address inputted from an exterior; and a register configured to output a true random number by latching an address corresponding to activation timing of the match signal among normal addresses. |
| 地址 |
Icheon-si Gyeonggi-do KR |
