| 摘要 |
An I/O control circuit, includes a mode setting unit configured to generate a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal in accordance with one of a plurality of I/O option modes, a first control signal generation unit configured to generate a first mode determination signal and a first control signal enable signal in response to the first I/O option signal and the first mode signal, and a second control signal generation unit configured to generate a second control signal enable signal, a third control signal enable signal, and a fourth control signal enable signal in response to a second I/O option signal, the first mode determination signal, the second mode signal, the third mode signal, and the fourth mode signal. |
| 主权项 |
1. A semiconductor memory device, comprising:
a mode control unit configured to generate an output signal in response to a first control signal enable signal, a second control signal enable signal, a third control signal enable signal, a fourth control signal enable signal, and a buffer enable signal received from an I/O control circuit; a pad unit comprising an I/O mode control pad, a data I/O pad, and a data I/O strobe pad; an input driving unit configured to be driven in response to the output signal of the mode control unit and electrically coupled to the pad unit; an output driving unit configured to be driven in response to the output signal of the mode control unit and electrically coupled to the pad unit; and an I/O conversion unit configured to provide a memory region with data received from the input driving unit and to provide the output driving unit with data received from the memory region in response to the fourth control signal enable signal. |
