Method And Apparatus For A Zero Voltage Processor Sleep State

摘要

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

主权项

1. A system comprising:
at least one processor comprising a first core and a second core; voltage regulation circuitry to regulate an operational voltage of the first core and the second core; an interconnect to couple one of the at least one processor to one or more system components; and a system memory coupled to one of the at least one processor, one of the at least one processor comprising:
the first core to execute sequences of instructions;the second core to execute sequences of instructions;a shared cache accessible by both the first core and the second core;power management logic to cause the first core to be powered down while the second core remains in an active state;wherein power to the shared cache is to be maintained to enable access by the second core; andwherein data associated with the first core is to be preserved when the first core is powered down.