OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU

摘要

A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

主权项

1. A system comprising:
a plurality of last level cache (LLC) regions; a plurality of cores coupled to one or more of the LLC regions; a memory interface circuit to couple the cores to a system memory; an accelerator interface to couple one or more of the cores to an accelerator device; wherein a core of the plurality of cores comprises:
a plurality of thermal sensors to collect thermal data for the core, anda plurality of performance counters to count architectural events within the core, at least one counter to count completed instructions; anda power management unit to manage power usage on a per core basis based on at least one of available power, thermal readings from the plurality of thermal sensors and/or architectural events counted by the performance counters, and to adjust a frequency of the core and to set a turbo mode based on the at least one available power.