发明名称 デュアルゲート構造の半導体装置およびその製造方法
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor device with a dual gate structure, having a structure capable of achieving simplification of manufacturing processes.SOLUTION: In first and second Nch MOSs, conductivity types of gate electrodes 12 are made to be reverse each other while P-type well regions 10 have the same channel concentration. In first and second Pch MOSs, conductivity types of gate electrodes 22 are made to be reverse each other while N-type well regions 20 have the same channel concentration. Thereby, in each of the Nch MOSs and the Pch MOSs, both MOS FETs one of which has depression characteristics and the other of which has enhancement characteristics can be configured only by reversing the conductivity types of the gate electrodes 12, 22. In a semiconductor device having such structure, the first and second Nch MOSs have the same channel concentration and the first and second Pch MOSs also have the same channel concentration, so that it becomes unnecessary to perform an ion injection process or the like for adjusting a threshold voltage Vt. Accordingly, simplification of manufacturing processes can be achieved.
申请公布号 JP6060718(B2) 申请公布日期 2017.01.18
申请号 JP20130026752 申请日期 2013.02.14
申请人 株式会社デンソー 发明人 櫻井 晋也;奥野 卓也
分类号 H01L21/8238;H01L21/28;H01L21/8236;H01L27/088;H01L27/092;H01L29/423;H01L29/49 主分类号 H01L21/8238
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