发明名称 調停回路、調停回路の制御方法、処理装置
摘要 PROBLEM TO BE SOLVED: To reduce power consumption.SOLUTION: Arbitration parts 32 to 35 arbitrate request signals to be output from processing parts 22a to 25c, and output request signals to an arbitration part 31 in accordance with the arbitration result. The arbitration part 31 arbitrates the request signals of processing parts 21a to 21f and the request signals of the arbitration parts 32 to 35, and outputs the request signals to a memory controller 28 in accordance with the arbitration result. Then, FIFO memories 41 to 48 perform data transfer between themselves and the arbitration parts 32 to 35 on the basis of clock signals CK2 to CK5, and perform data transfer between themselves and the arbitration part 31 on the basis of a clock signal CK1. A monitor part 51 monitors the transfer quantity of the arbitration part 31 and the transfer quantity of the arbitration parts 32 to 35. A transfer control part 52 generates a selection signal on the basis of the monitor result of the monitor part 51. A clock control part 26 changes the frequency of the clock signal CK2 in accordance with the selection signal.
申请公布号 JP6060788(B2) 申请公布日期 2017.01.18
申请号 JP20130085969 申请日期 2013.04.16
申请人 株式会社ソシオネクスト 发明人 岡田 雅樹
分类号 G06F13/362;G06F13/42 主分类号 G06F13/362
代理机构 代理人
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