发明名称 半導体装置
摘要 An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.
申请公布号 JP6063504(B2) 申请公布日期 2017.01.18
申请号 JP20150066394 申请日期 2015.03.27
申请人 株式会社半導体エネルギー研究所 发明人 山崎 舜平;細羽 みゆき;坂田 淳一郎;桑原 秀明
分类号 H01L29/786;G02F1/1368;G09F9/30;H01L21/336;H01L21/8234;H01L27/06;H01L27/08;H01L51/50;H05B33/14 主分类号 H01L29/786
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