| 摘要 |
The present invention relates to an all-digital Phase-Locked Loop comprising
- a reference phase generator (PHR) arranged for receiving a digital signal and for splitting the digital signal into an integer part (PHR_I) and a fractional part (PHR_F),
- an estimator block (20) arranged for estimating a control signal,
- a digital-to-time converter (30) arranged for receiving the estimated control signal and a reference clock signal (FREF) and arranged for deriving a delayed reference clock signal () using the reference clock signal and the estimated control signal,
- a time-to-digital converter (40) arranged for receiving the delayed reference clock signal and a desired clock signal phase () and for deriving a fractional phase error,
characterised in that the estimator block is arranged for receiving the fractional phase error and for determining the estimated control signal by
* correlating the fractional phase error with a version () of said fractional part having zero mean, yielding a correlated signal (),
* multiplying the correlated signal with its absolute value,
* integrating the outcome () of said multiplying to so obtain the estimated control signal. |
