发明名称 Vertical nanowire transistor with axially engineered semiconductor and gate metallization
摘要 Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.
申请公布号 GB201620747(D0) 申请公布日期 2017.01.18
申请号 GB20160020747 申请日期 2013.06.24
申请人 Intel Corporation 发明人
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