Method for manufacturing a digital circuit and digital circuit

摘要

A method for manufacturing a digital circuit is described including forming a plurality of field effect transistor pairs, connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal and setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition.

主权项

1. A method for manufacturing a digital circuit comprising:
forming a plurality of field effect transistor pairs; connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal; setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition; forming one or more pairs of competing paths such that, for each field effect transistor pair, the two field effect transistors are in different competing paths of a pair of competing paths; and connecting the one or more pairs of competing paths and the nodes such that for each pair of competing paths, the competing paths are connected to different ones of the two nodes and the electrical state of the node connected to one of the competing paths is fed back to the other of the competing paths to hinder it in a competition of the competing paths.