IR enabled gating of TAP and WSP shift, capture, transfer

摘要

In a first embodiment a Test Access Port (TAP) of IEEE standard 1149.1 is allowed to commandeer control from a Wrapper Serial Port (WSP) of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC (Auxiliary Test Control bus) or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

主权项

1. A circuit comprising:
A. a TDI lead, a TDO lead, a TMS lead, and a TCK lead; B. a wrapper serial port interface having a Capture lead, a Shift lead, a Transfer lead, a WSI lead, and a WSO lead; C. test access port controller circuitry having inputs connected to the TMS and TCK leads and having a ClockDR output, a CaptureDR State output, and a ShiftDR State output; D. instruction register circuitry having:
a. a TDI input coupled to the TDI lead;b. an auxiliary enable output;c. a functional clock input;d. a ClockDR input coupled with the ClockDR output;e. a first Clock output coupled with the functional clock input and the ClockDR input;f. a second Clock output coupled with the ClockDR input;g. a gated Capture input and a Capture output coupled with the gated capture input and a first logic state;h. a gated Shift input and a first Shift output selectively coupled with the gated Shift input and a second logic state;i. a second Shift output coupled with the Shift DR State output; andj. a gated Transfer input and a first Transfer output coupled to the gated Transfer input; E. a first scan cell having;
a. a first Clock input coupled to the first Clock output;b. a Capture input coupled to the Capture output;c. a first Shift input coupled to the first Shift output;d. a first TDI input coupled to the TDI lead and the WSI lead; ande. a first TDO output; F. a second scan cell having;
a. a second Clock input coupled to the second Clock output;b. a second Shift input coupled to the second Shift output;c. a first Transfer input coupled to the first Transfer output;d. a second TDI input coupled to the first TDO output; ande. a second TDO output coupled to the TDO lead and the WSO lead; and G. gating circuitry having:
a. a CaptureDR input coupled to the CaptureDR State output;b. a Capture input coupled to the Capture lead;c. a gated Capture output coupled to the CaptureDR input and the Capture input and coupled to the gated Capture input;d. a ShiftDR input coupled to the ShiftDR State output;e. a Shift input coupled to the Shift lead;f. a gated Shift output coupled to the Shift DR input and the Shift input and coupled to the gated Shift input;g. a Transfer input coupled to the Transfer lead;h. an auxiliary enable input coupled to the auxiliary enable output; andi. a gated Transfer output coupled to the Transfer input and the auxiliary enable input and coupled to the gated Transfer input.