发明名称 Methods, apparatus, and system for using filler cells in design of integrated circuit devices
摘要 At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout.
申请公布号 US9547741(B2) 申请公布日期 2017.01.17
申请号 US201414518939 申请日期 2014.10.20
申请人 GLOBALFOUNDRIES INC. 发明人 Schroeder Uwe Paul;Davar Sushama
分类号 G06F17/50;H01L29/06;H01L29/66 主分类号 G06F17/50
代理机构 Williams Morgan, P.C. 代理人 Williams Morgan, P.C.
主权项 1. A method for providing a layout for an integrated circuit device, comprising: receiving a design for an integrated circuit device, wherein said design comprises a first functional cell and a second functional cell; placing said first functional cell on a circuit layout; determining whether said first cell comprises a vertical boundary that is electrically floating; placing a filler cell adjacent to said vertical boundary on said circuit layout in response to determining that said first cell comprises said vertical boundary that is electrically floating; placing said second functional cell adjacent to said filler cell to form a contiguous active area on said circuit layout, fabricating, by a semiconductor device processing system, said integrated circuit device based upon said circuit layout.
地址 Grand Cayman KY