Self-timed user-extension instructions for a processing device

摘要

A processor for executing configurable instructions and a method of configuring the processor are disclosed. In one embodiment, the processor includes (i) a processor core to execute preconfigured instructions and (ii) a processor core extension to execute user-defined extension instructions that are configurable instructions. The user-defined extension instructions may include an autonomous instruction with varying execution cycles based on source data and an operation performed. The processor core extension employs extension interface signals as a handshake protocol to operate together with the processor core without knowing any priori knowledge of how many processor clock cycles that the autonomous instruction will take to complete.

主权项

1. A method for configuring a processor core extension for executing an autonomous instruction, the method comprising:
receiving, using a user interface, extension configuration information defining the processor core extension, the extension configuration information describing an autonomous extension instruction and information about at least one of registers and condition codes of the processor core extension; identifying candidate interface signals for communicating via an extension interface between a processor core and extension logic in the processor core extension that processes the autonomous instruction in accordance with the extension configuration information, the identified candidate interface signals including a ready status signal indicating that the extension logic is ready to provide a result of the autonomous instruction to the processor core; generating, for display on the user interface, a list of the identified candidate interface signals and information about one or more of the identified candidate interface signals; receiving a selection of a set of interface signals to be processed by the extension interface from the list of the identified candidate interface signals, the set of interface signals including the ready status signal and one or more additional interface signals; generating a digital representation of the extension logic to process the autonomous instruction according to the extension configuration information; and generating a digital representation of extension interface logic to process the selected set of interface signals.