Asymmetric full duplex communication including device power communication

摘要

An active transceiver circuit for transmission of a low bitrate data signal over and reception of a high bitrate data signal from a single ended transmission medium is provided. The active transceiver circuit includes an input port for receiving a low bitrate input data signal, an output port for delivering a high bitrate output data signal, a differential input/output port for launching a low bitrate data signal into the single ended transmission medium and for receiving a high bitrate data signal from the single ended transmission medium, a first and second single ended output driver adapted for each delivering, on their respective output nodes, the shaped low bitrate input data signal, and a high bitrate receiver for receiving the signals at output nodes of the first and second single ended output drivers, and for generating a high bitrate output data signal on the output port.

主权项

1. An active transceiver circuit for an electrical communication system using wires or coaxial cables for full duplex transmission of a high bitrate data signal over and reception of a low bitrate data signal from a single ended transmission medium, the transceiver circuit comprising:
an input port configured to receive a high bitrate input data signal, an output port configured to deliver a low bitrate output data signal, wherein the output port is different from the input port, a differential input/output port configured to launch a high bitrate data signal into the single ended transmission medium and to receive a low bitrate data signal from the single ended transmission medium, wherein the low bitrate data signal has a bitrate which is at least 3 times lower than the high bitrate data signal, a differential output driver configured to receive the differential high bitrate input data signal and transmit this signal to the differential input/output port, an averaging circuit configured to perform at least averaging of the signals at output nodes of the differential output driver, and low pass filtering of the averaged signal, and a signal restore circuit configured to receive the low pass filtered average signal from the averaging circuit and for generating therefrom a restored low bitrate output data signal on the output port, wherein the averaging circuit comprises at least two resistors, each resistor being separately coupled to each output node of the differential output driver, and wherein the outputs of the at least two resistors are coupled to a common node.