发明名称 |
Thermal treatment for reducing transistor performance variation in ferroelectric memories |
摘要 |
Thermal treatment of a semiconductor wafer in the fabrication of integrated circuits including MOS transistors and ferroelectric capacitors, including those using lead-zirconium-titanate (PZT) ferroelectric material, to reduce variation in the electrical characteristics of the transistors. Thermal treatment of the wafer in a nitrogen-bearing atmosphere in which hydrogen is essentially absent is performed after formation of the transistors and capacitor. An optional thermal treatment of the wafer in a hydrogen-bearing atmosphere prior to deposition of the ferroelectric treatment may be performed. |
申请公布号 |
US9548377(B2) |
申请公布日期 |
2017.01.17 |
申请号 |
US201414273704 |
申请日期 |
2014.05.09 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
Udayakumar Kezhakkedath R.;San Kemal Tamer |
分类号 |
H01L29/66;H01L21/324;H01L27/115;H01L49/02 |
主分类号 |
H01L29/66 |
代理机构 |
|
代理人 |
Keagy Rose Alyssa;Brill Charles A.;Cimino Frank D. |
主权项 |
1. A method of fabricating an integrated circuit, comprising the steps of:
forming at least one metal-oxide-semiconductor (MOS) transistor near a semiconducting surface of a body; then forming at least one ferroelectric capacitor near the surface of the body; forming an interlevel dielectric layer and a conductor level above the at least one ferroelectric capacitor; then thermally treating the body in a non-hydrogen-bearing atmosphere that includes a nitrogen-bearing gas; and then depositing a protective overcoat layer; wherein no thermal treatment is performed after the step of depositing the protective overcoat layer. |
地址 |
Dallas TX US |