Compact CMOS device isolation

摘要

An integrated circuit includes a first well of the first conductivity type formed in a semiconductor layer where the first well housing active devices and being connected to a first well potential, a second well of a second conductivity type formed in the semiconductor layer and encircling the first well where the second well housing active devices and being connected to a second well potential, and a buried layer of the second conductivity type formed under the first well and overlapping at least partially the second well encircling the first well. In an alternate embodiment, instead of the buried layer, the integrated circuit includes a third well of the second conductivity type formed in the semiconductor layer where the third well contains the first well and overlaps at least partially the second well encircling the first well.

主权项

1. An integrated circuit, comprising:
a semiconductor layer of a first conductivity type and being lightly doped; a first well of the first conductivity type formed in the semiconductor layer, the first well housing active devices and being connected to a first well potential, a second well of a second conductivity type formed in the semiconductor layer and having a closed loop well structure to encircle the first well, the second well housing active devices and being connected to a second well potential; and a buried layer of the second conductivity type formed under the first well and the second well, the buried layer being formed overlapping at least partially the second well encircling the first well and the buried layer being formed under the second well to surround the periphery of the first well, the first well being isolated from the semiconductor layer by the second well and the buried layer surrounding the first well.