Integrated circuit defect detection and repair

摘要

In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.

主权项

1. A memory controller for use with a memory having memory cells arranged in rows and columns of memory cells including spare memory cells, comprising:
an internal self-test logic circuit built in within the memory controller, the self-test logic circuit including: a test pattern generator for generating test patterns and for testing memory cells within the memory using the generated test patterns; wherein the test pattern generator includes a plurality of generators including at least one instruction programmable address generator, at least one instruction programmable data generator, and a loop sequencer circuit adapted to apply to the generators a plurality of nested loop instructions, including a sequential loop of address instructions in a sequence of address instructions to the instruction programmable address generator, and to apply to the instruction programmable data generator, a sequential loop of data instructions in a sequence of data instructions nested within the sequential loop of address instructions, wherein the instruction programmable address generator is configured to generate a pattern of memory cell addresses in response to an address instruction being executed in sequence in the loop of address instructions to traverse a memory region of a plurality of memory cells, and wherein each memory cell address includes a row address of row address bits and a column address of column bits and wherein at least one instruction programmable data generator is configured to generate in response to a data instruction being executed in sequence in the loop of data instructions nested within the sequential loop of address instructions, a pattern of data for a pattern of test data, to be written in memory cells addressed by a pattern of memory cell addresses generated by the address generator wherein the generated pattern of data is a selectable function of the pattern of memory cell addresses of the memory cells in which the generated pattern of data is to be written.