| 主权项 |
1. A method of providing a dynamic random access memory (DRAM) integrated circuit, comprising:
providing an external signal interface, comprising:
a plurality of interface circuits, wherein:
each interface circuit is adapted to be coupled to an external signal line for the input and output of binary external data, wherein a first voltage range on the external signal line corresponds to a first binary logic state and a second voltage range on the external signal line corresponds to a second binary logic state, andthe logic polarity of the external data is statistically distributed to favor the first binary logic state; providing a memory array, comprising:
a plurality of memory cells, wherein:
each memory cell comprises a data storage capacitor, wherein charging the capacitor to a third voltage range corresponds to a third binary logic state and charging the capacitor to a fourth voltage range corresponds to a fourth binary logic state,a leakage current in each memory cell is substantially larger when its capacitor charged to the third voltage range, andthe leakage current in each memory cell is substantially smaller when its capacitor charged to the fourth voltage range; and providing a plurality of selective inversion circuits coupled between the plurality of interface circuits and the memory array and adapted to minimize the leakage current of the memory array, wherein:
external data is stored in the array such that data in the first binary logic state is stored in each memory cell as the fourth binary logic state and the second binary logic state is stored in a memory cell as the third binary logic state. |
