Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features

摘要

Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them.

主权项

1. A sensing circuit for a flash memory device comprising:
a reference column including a reference voltage node, a reference memory cell, a first differential threshold PMOS transistor that is diode-connected and has a drain connected to the reference voltage node, and a first differential threshold NMOS transistor having a drain connected to the reference voltage node; circuitry comprising a comparator that includes a second differential threshold NMOS transistor having a gate connected to a reference voltage line and a source connected to a first node, a third differential threshold NMOS transistor having a drain connected to the first node, a second differential threshold PMOS transistor that is diode-connected and has a drain connected to a second node, a third differential threshold PMOS transistor having a gate connected to the second node and a drain connected to a third node, a fourth differential threshold NMOS transistor having a source connected to the first node, a fourth differential threshold PMOS transistor having a gate connected to the third node and a drain connected to an output node, and a fifth differential threshold NMOS transistor having a drain connected to the output node, wherein gates of the fourth and fifth differential threshold NMOS transistors are connected to a common control line; wherein one or more of the differential threshold transistors are transistors that each have a gate-to-source threshold voltage that differs from a gate-to-drain threshold voltage; and wherein one or more of the differential threshold transistors comprises:
a substrate of semiconductor material of a first conductivity type;a first region and a second region in the substrate, wherein the first and second regions are of a second conductivity type and spaced apart from each other defining a channel region therebetween;an insulating layer disposed over the channel region of the substrate, wherein the insulating layer comprises opposed insulating portions including a first insulating portion adjacent the first region and a second insulating portion adjacent the second region; anda gate portion above the insulating layer;wherein each insulating portion characterizes a threshold voltage between the gate and the first region or the second region adjacent each insulating portion; andwherein the first insulating portion is fabricated with varying dimension including a first thickness different than a second thickness of the second insulating portion to provide a first threshold voltage that differs from a second threshold voltage associated with the opposed insulating portion.