发明名称 |
Semiconductor device and information reading method |
摘要 |
A semiconductor device including a memory device configured to take a plurality of resistance states that are distinguishable from one another; a bias application section configured to apply, in a bias application period, a bias signal to the memory device; and a determination section configured to determine a resistance state of the memory device on the basis of a detection signal, in which the detection signal is generated in the memory device to which the bias signal is applied. The bias application section sets a length of the bias application period in accordance with a resistance value of the memory device, when the resistance state determined by the determination section is predetermined one of the resistance states. |
申请公布号 |
US9548112(B2) |
申请公布日期 |
2017.01.17 |
申请号 |
US201514934630 |
申请日期 |
2015.11.06 |
申请人 |
SONY SEMICONDUCTOR SOLUTIONS CORPORATION |
发明人 |
Shiimoto Tsunenori |
分类号 |
G11C11/00;G11C13/00 |
主分类号 |
G11C11/00 |
代理机构 |
Dentons US LLP |
代理人 |
Dentons US LLP |
主权项 |
1. A memory system, comprising:
a plurality of memory cells configured to have a plurality of resistance states; a first driving section configured to connect to the memory cells via first lines; a second driving section configured to connect to the memory cells via second lines and include a read section that applies a bias signal via the second lines to the memory cells and a determination section determining one of the plurality of resistance states of the memory device; and a control section configured to control the memory cells, wherein, the second driving section sets a length of a bias period in accordance with a resistance value of the memory cells based on the resistance state determined by the determination section. |
地址 |
Kanagawa JP |