Timing exact design conversions from FPGA to ASIC

摘要

A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.

主权项

1. A field-programmable gate array (FPGA) design conversion to an application-specific integrated circuit (ASIC), the conversion comprising:
providing an FPGA device and an ASIC device having:
a substantially identical layout;substantially identical transistors and one or more metal layer layouts; andsubstantially identical timing characteristics; providing a user-configurable memory to program transistors in the FPGA; providing a mask-configurable memory to program transistors in the ASIC; and in a processor, converting a user-configurable memory bit pattern, to thereby program the transistors of the FPGA, to a mask-configurable memory pattern comprising a conductive pattern deposited to hard-wire logic connections in an adjacent layer of digital circuits to only Vcc and Vss, wherein the digital circuits comprise the transistors of the ASIC, in order to identically program the transistors of the ASIC.