发明名称 Interrupt supervision system, processing system and method for interrupt supervision
摘要 An interrupt supervision system comprises an interrupt controller device comprising a plurality of interrupt request input lines and at least one output line connectable to a processing device. The interrupt controller device is arranged to receive, on the plurality of interrupt request input lines, a plurality of corresponding interrupt requests and to provide, on the at least one output line, the plurality of interrupt requests to the processing device in a sequence generated by the interrupt controller device depending on one or more priorities assigned to the interrupt requests; and one or more interrupt checker devices, each being arranged to receive a reception indication when the interrupt controller device receives, on a selected one of the plurality of interrupt request lines, a corresponding selected interrupt request, and to provide a corresponding error indication when an output of the corresponding selected interrupt request from the interrupt controller device on the at least one output line is not confirmed within a latency period assigned to the corresponding selected interrupt request, wherein the assigned latency period begins when the interrupt checker device receives the reception indication.
申请公布号 US9547546(B2) 申请公布日期 2017.01.17
申请号 US201214382593 申请日期 2012.03.12
申请人 NXP USA, Inc. 发明人 Baumeister Markus;Freeman Jeffrey L.
分类号 G06F11/00;G06F11/07;G06F13/24 主分类号 G06F11/00
代理机构 代理人
主权项 1. An interrupt supervision system, comprising: a plurality of interrupt request input lines; an interrupt request output line; an interrupt controller device connected to said interrupt request input lines, for receiving, on said plurality of interrupt request input lines, a plurality of interrupt requests, said interrupt controller device being arranged to generate a sequence of interrupt requests from said plurality of interrupt requests depending on one or more priorities assigned to said interrupt requests and to output said plurality of interrupt requests in said sequence on said interrupt request output line; said interrupt supervision system further comprising an interrupt checker device connected to a selected one of said interrupt request input lines, to detect that said interrupt controller device has received on said selected interrupt request input line a selected interrupt request, and connected to said interrupt request output line; said interrupt checker device being arranged to provide an error indication when an output of said selected interrupt request on said interrupt request output line has not been confirmed within a latency period assigned to said selected interrupt request, said latency period beginning when said interrupt checker device detects that said interrupt controller device has received said selected interrupt request.
地址 Austin TX US