Selectively scheduling memory accesses in parallel based on access speeds of memory

摘要

Devices, systems, methods, and other embodiments associated with selectively scheduling memory accesses in parallel are described. In one embodiment, a method includes determining, by a hardware controller, an access speed associated with a page request. The page request is a request to access a memory page in a memory device. The access speed is a number of clock cycles used to access the memory page addressed by the page request. The method also includes scheduling when the page request will be executed based, at least in part, on the access speed by assigning the page request to be executed in parallel with at least one other page request that is to access a different memory page in the memory device using a same number of clock cycles as the page request.

主权项

1. A method, comprising:
determining, by a hardware controller, an access speed associated with a page request according to a memory address associated with the page request, wherein the page request is a request to access a memory page in a memory device, wherein the memory device includes memory cells consisting of multi-level memory cells (MLCs) forming a plurality of memory pages, wherein the access speed is a number of clock cycles used to access the memory page addressed by the page request, and wherein the plurality of memory pages in the multi-level memory cells include memory pages with different access speeds according to whether a memory page is comprised of most significant bits of the multi-level memory cells or least significant bits of the multi-level memory cells; and scheduling execution for the page request according to the access speed determined for the memory page associated with the page request by assigning the page request to be executed in parallel with at least one other page request that is to access a different memory page of the plurality of memory pages using a same number of clock cycles as the page request, wherein scheduling when the page request will be executed includes aligning the page request and the at least one other page request in a queue and controlling the page request and the at least one other page request to be executed in parallel, wherein scheduling when the page request will be executed includes scheduling when the page request will access the memory device that includes memory cells that are multiple level cells that have a same bit density.