Dual fill silicon-on-nothing field effect transistor

摘要

A patterned stack of a first silicon-germanium alloy nanowire, a second silicon-germanium alloy nanowire, and a silicon-containing nanowire is formed on a substrate. After formation of a first dielectric isolation layer around the patterned stack, a disposable gate structure can be formed. End portions of the second silicon-germanium alloy nanowire are removed to form first cavities underlying end portions of the silicon-containing nanowire. Dielectric nanowires are formed in cavities concurrently with formation of a gate spacer. After recessing the first dielectric isolation layer, a second cavity is formed by removing the first silicon-germanium alloy nanowire. The second cavity is filled with a second dielectric isolation layer, and raised active regions can be formed by a selective epitaxy process. After formation of a planarization dielectric layer, the disposable gate structure and the remaining portion of the second silicon-germanium alloy nanowire with a replacement gate structure.

主权项

1. A semiconductor structure comprising:
at least one dielectric isolation layer located on a substrate; a silicon-containing nanowire containing a source region located at one end of a body region and a drain region located at another end of said body region, said silicon-containing nanowire is located above and spaced apart from said at least one dielectric isolation layer; a pair of dielectric nanowires laterally spaced from each other, and contacting a bottom surface of said source region and said drain region of said silicon-containing nanowire and a top surface of said at least one dielectric isolation layer; and a gate structure including a gate dielectric and a gate electrode, said gate structure encircling said body region of said silicon-containing nanowire.