Identifying inversion error in logic equivalence check

摘要

System and method of checking logic equivalence following flip-flop insertions to identify paths with inversion errors. All the flip-flops in a gate-level netlist and the corresponding RTL design are treated as buffers in a logic equivalence check (LEC) tool. A logic mismatch of a path between the RTL design and the netlist indicates an odd number of inverters have been inserted in the path during a flip-flop insertion process. Accordingly, the identified path is adjusted to ensure an even number of inverters.

主权项

1. A computer implemented method, performed by a processor, for logic equivalence checking, said processor is coupled to memory which stores instructions that, when executed by said processor, cause said processor to perform said method comprising:
accessing a first register-transfer level (RTL) design of an integrated circuit comprising a plurality of interconnects, wherein a respective interconnect in said first RTL design comprises a first plurality of flip-flops; accessing a first physical implementation of said integrated circuit, wherein said first physical implementation comprises said plurality of interconnects, wherein said respective interconnect in said first physical implementation comprises a second plurality of flip-flops, inverters, and buffers; replacing said first plurality of flip-flops with buffers to generate a second RTL design; replacing said second plurality of flip-flops with buffers to generate a second physical implementation; checking logic equivalence between said second RTL design and said second physical implementation; and identifying a logic error in said first physical implementation based on said checking.