Systems and methods for reconfiguring cache memory

摘要

A microprocessor system is disclosed that includes a first data cache that is shared by a first group of one or more program threads in a multi-thread mode and used by one program thread in a single-thread mode. A second data cache is shared by a second group of one or more program threads in the multi-thread mode and is used as a victim cache for the first data cache in the single-thread mode.

主权项

1. A method comprising:
in a computer system executing multiple program threads in multi-thread mode in a processing unit:
accessing a first Level 1 (L1) data cache for a first subset of the threads;accessing a second L1 data cache for a second subset of the threads; in the computer system executing a single program thread in single thread mode in the processing unit:
configuring the second L1 data cache as a victim cache for the first L1 data cache upon switching to the single thread mode; andaccessing the first L1 data cache and the victim cache for the single program thread; in the single thread mode, storing the same information in a first memory management unit (MMU) coupled between a first load/store execution unit and the first L1 data cache, and a second MMU coupled between a second load/store execution unit and the second L1 data cache.