| 摘要 |
An arithmetic processing device for executing the arithmetic of a convolutional neural network, the arithmetic processing device being provided with a plurality of systolic array cells (21), a plurality of input switches (22), a plurality of output switches (23), a convolution arithmetic control unit, and a total binding arithmetic control unit. The plurality of input switches (22), provided corresponding to each of the plurality of systolic array cells (21), have input terminals (22a, 22b) and an output terminal (22c), and are switched to one of a state in which the input terminal (22a) and the output terminal (22c) are connected and a state in which the input terminal (22b) and the output terminal (22c) are connected. The plurality of output switches (23), provided corresponding to each of the plurality of systolic array cells (21), have an input terminal (23a) and output terminals (23b, 23c), and are switched to one of a state in which the input terminal (23a) and the output terminal (23b) are connected and a state in which the input terminal (23a) and the output terminal (23c) are connected. |
