发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 A semiconductor memory device includes string select lines extending in a first direction, vertical pillars connected to the string select lines, sub-interconnections on the string select lines, bitlines connected to the vertical pillars through the sub-interconnections, and upper contact plugs connecting the sub-interconnections to the bitlines. The string select lines include odd and even string select lines alternately arranged in a second direction. The sub-interconnections each connect a pair of vertical pillars respectively connected to one of the odd string select lines and one of the even string select lines that are adjacent to each other. Each of the upper contact plugs is between one of the sub-interconnections and one of the bitlines. Each of the upper contact plugs is arranged more adjacent to one string select line of the adjacent string select lines to which the pair of vertical pillars connected by the sub-interconnections are connected.
申请公布号 US2017012052(A1) 申请公布日期 2017.01.12
申请号 US201615097485 申请日期 2016.04.13
申请人 Samsung Electronics Co., Ltd. 发明人 JANG WON-CHUL;Kim Hong-soo;Cho Tae-keun
分类号 H01L27/115;H01L23/522;G11C16/04;G11C16/08;G11C16/26;H01L29/788;H01L27/24;H01L45/00;H01L27/22;H01L43/08;H01L43/10;G11C11/16;H01L23/528;G11C16/10 主分类号 H01L27/115
代理机构 代理人
主权项 1. A semiconductor memory device comprising: string select lines extending in a first direction, the string select lines including odd string select lines alternately arranged with even string select lines in a second direction that intersects the first direction; a plurality of vertical pillars connected to the string select lines; sub-interconnections on the string select lines, the sub-interconnections each connecting a pair of vertical pillars that respectively are connected to one of the odd string select lines and one of the even string select lines that are adjacent to each other from among the string select lines; bitlines connected to the plurality of vertical pillars through the sub-interconnections, the bitlines extending in the second direction; and upper contact plugs connecting the sub-interconnections to the bitlines, each of the upper contact plugs being between one of the sub-interconnections and one of the bitlines,a distance between each corresponding one of the upper contact plugs and one of the odd and even string select lines connected by a corresponding one of the sub-interconnections being less than a distance between the corresponding one of the upper contact plugs and an other one of the odd and even string select lines connected to the corresponding one of the sub-interconnections.
地址 Suwon-si KR