发明名称 SEMICONDUCTOR DEVICE HAVING INTERCONNECTION STRUCTURE
摘要 A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.
申请公布号 US2017011996(A1) 申请公布日期 2017.01.12
申请号 US201615201922 申请日期 2016.07.05
申请人 LEE Dohyun;Park Youngwoo;Park Junghoon;Lee Jaeduk 发明人 LEE Dohyun;Park Youngwoo;Park Junghoon;Lee Jaeduk
分类号 H01L23/528;H01L23/522;H01L21/768;H01L27/115 主分类号 H01L23/528
代理机构 代理人
主权项 1. A semiconductor device comprising: a semiconductor substrate; a semiconductor pattern on the semiconductor substrate; a three-dimensional memory array on the semiconductor pattern; and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate, the peripheral interconnection structure including an upper interconnection structure and a lower interconnection structure, the lower interconnection structure being under the upper interconnection structure, the upper interconnection structure including an upper interconnection and an upper barrier layer, the lower interconnection structure including a lower interconnection and a lower barrier layer, the upper barrier layer being under a bottom surface of the upper interconnection, the upper barrier layer does not cover side surfaces of the upper interconnection, the lower barrier layer is under a bottom surface of the lower interconnection, the lower barrier layer covers side surfaces of the lower interconnection.
地址 Hwaseong-si KR