WIDE TEMPERATURE RANGE PEAK HOLD CIRCUIT

摘要

A peak hold circuit configured for use in a downhole sensor includes a long tail pair circuit, a correction circuit, and a current mirror circuit. The current mirror circuit includes two current mirrors connected to a long tail pair formed by a first transistor and a second transistor. The current mirror also includes a first resistor and a second resistor connected to a third transistor. The first transistor is connected to a correction transistor of the correction circuit. The value of the first resistor is selected to be essentially equal to the same value as the second resistor so that when the long tail pair is balanced, the current flowing through a collector of the second transistor is equal to the current flowing through the first transistor, causing the correction transistor to switch off.

主权项

1. A peak hold circuit comprising:
a long tail pair circuit comprising:
a first transistor provided with an input signal;a second transistor, wherein a second emitter of the second transistor is coupled to a first emitter of the first transistor; anda first current source coupled to a low voltage source; a correction circuit comprising:
a hold capacitor which holds a hold voltage;an operational amplifier supplied with the hold voltage; anda correction transistor, comprising a correction base, a correction collector and a correction emitter, wherein the correction collector is coupled to the hold capacitor and the operational amplifier, and the correction emitter is coupled to a high voltage source; a current mirror circuit comprising:
a second current source comprising a second input, a second output, and a second common node, wherein the second input is coupled to a third emitter of a third transistor via a first resistor, the second output is coupled to a first collector of the first transistor, and the second common node is coupled to the high voltage source; anda third current source comprising a third input, a third output, and a third common node, wherein the third input is coupled to a third emitter of the third transistor via a second resistor and to ground via a third resistor, and the third output is coupled to a second collector of the second transistor, and the third common node is coupled to the high voltage source;
wherein the second output of the second current source and the first collector of the first transistor are coupled to the correction base of the correction transistor.