DUAL NON-VOLATILE MEMORY CELL COMPRISING AN ERASE TRANSISTOR

摘要

The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.

主权项

1. A method, comprising:
manufacturing on a semiconductor substrate a memory cell that includes:
a first floating-gate transistor having a control gate, a floating gate, and a drain region;a second floating-gate transistor having a control gate, a floating gate, and a drain region, wherein:the floating gates of the first and second floating-gate transistors are electrically coupled to each other, and the second floating-gate transistor comprises:
a tunnel dielectric layer extending along the floating gate of the second floating-gate transistor; anda permanently conductive region electrically coupled to the drain region of the second floating-gate transistor and extending along an opposite side of the tunnel dielectric layer with respect to the floating gate of the second floating-gate transistor, the method comprising: forming in the substrate isolating trenches delimiting first and second strips of the substrate, making the second strip permanently conductive by doping the second strip, forming a first dielectric layer on the substrate and forming the floating gate of the first floating gate transistor on the first dielectric layer, the floating gate being arranged transversally to the two strips of substrate, forming a second dielectric layer on the floating gate of the first floating gate transistor and forming the control gate of the first floating gate transistor on the floating gate with of the first floating gate transistor, to obtain a gate stack, and doping the first and second strips of substrate on opposite sides of the gate stack, thereby generating drain and source regions of the first floating-gate transistor and a drain region of the second floating-gate transistor, the permanently conducting region opposite the floating gate of the second floating-gate transistor being formed by a region of the second strip, which is doped before forming the gate stack.