发明名称 GERMANIUM-BASED QUANTUM WELL DEVICES
摘要 A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
申请公布号 US2017012116(A1) 申请公布日期 2017.01.12
申请号 US201615270795 申请日期 2016.09.20
申请人 Intel Corporation 发明人 Pillarisetty Ravi;Jin Been-Yih;Chu-Kung Benjamin;Metz Matthew V.;Kavalieros Jack T.;Radosavljevic Marko;Kotlyar Roza;Rachmady Willy;Mukherjee Niloy;Dewey Gilbert;Chau Robert S.
分类号 H01L29/775;H01L29/66;H01L27/088;H01L29/267;H01L29/06 主分类号 H01L29/775
代理机构 代理人
主权项 1. A microelectronic device, comprising: a germanium quantum well channel region transistor, comprising: a lower barrier region;a germanium channel region on the lower barrier region;an upper barrier region on the germanium channel region;a gate dielectric on the upper barrier region; anda gate electrode on the gate dielectric; a group III-V material quantum well channel region transistor, comprising: a lower barrier region;a group III-V material channel region on the lower barrier region;an upper barrier region on the germanium channel region;a gate dielectric on the upper barrier region; anda gate electrode on the gate dielectric; and an isolation region disposed between the germanium quantum well region transistor and the group III-V material quantum well channel region transistor.
地址 Santa Clara CA US