Providing State Storage in a Processor for System Management Mode

摘要

In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

主权项

1. A system comprising:
a first processor including a first core to execute instructions and to enter a system management mode (SMM), a first indicator to indicate whether a thread executing on the first core is in a long flow operation, a second indicator to indicate whether the thread is in a system management interrupt (SMI)-inhibited state, and a storage unit, wherein upon entry to the SMM the first core is to store an active state present in a state storage of the first core into the storage unit and to store a SMM execution state into the state storage, the storage unit dedicated to storage of the active state during the SMM; a second processor including a second core to execute instructions and to enter the SMM, a first indicator to indicate whether a second thread executing on the second core is in a long flow operation, a second indicator to indicate whether the second thread is in the SMI-inhibited state, and a second storage unit, wherein upon entry to the SMM the second core is to store an active state present in a state storage of the second core into the second storage unit and to store a SMM execution state into the state storage, the second storage unit dedicated to storage of the active state during the SMM; and a dynamic random access memory (DRAM) coupled to the first and second processors, wherein a portion of the DRAM is a system management random access memory (SMRAM) for the system.