| 摘要 |
An SRAM is provided with two Si columns (5a, 5b) on a substrate. An inverter circuit is formed in each of the Si columns, said circuit comprising a drive N-channel SGT that has a first N＋ layer (9a) and a second N＋ layer (32a, 32b) as a source and a drain, and a load SGT that has a first P＋ layer (52a, 52b) and a second P＋ layer (33a, 33b) as a source and a drain. A selection SGT having a third N＋ layer (64a, 64b) and a fourth N＋ layer (53a, 53b) is formed on the top of an SiO2 layer (2a, 2b) provided on the top of the inverter circuit. The first N＋ layer is connected to a ground wiring metal layer (VSS), the first P＋ layer is connected to a power source wiring metal layer (VDD) with a NiSi layer (49a) interposed therebetween, a gate TiN layer (12a, 12b) is connected to a word wiring metal layer (WL) with a NiSi layer (60) interposed therebetween, and the third N＋ layer is connected to a reverse bit metal layer (RBL) and a bit metal layer (BL). |
