LEVEL CONVERTER CIRCUIT

摘要

A level conversion circuit includes: first P-ch and N-ch transistors and second P-ch and N-ch transistors respectively connected in series between first and second power sources; third and fourth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and the drain of the first and second P-ch transistors; and fifth and sixth P-ch transistors respectively connected between the gates of the second and first P-ch transistors and a third power source, wherein differential input signals are applied to the gates of the first and second N-ch transistors, a bias voltage is applied to the gates of the third and fourth P-ch transistors, the gate of the fifth and sixth P-ch transistors are respectively connected to connection nodes of the first P-ch and N-ch transistors the second P-ch and N-ch transistors.

主权项

1. A level conversion circuit comprising:
a first P-ch transistor and a first N-ch transistor connected in series between a first power source and a second power source whose voltage is lower than the voltage of the first power source; a second P-ch transistor and a second N-ch transistor connected in series between the first power source and the second power source; a third P-ch transistor connected between the gate of the second P-ch transistor and the drain of the first P-ch transistor; a fourth P-ch transistor connected between the gate of the first P-ch transistor and the drain of the second P-ch transistor; a fifth P-ch transistor connected between the gate of the second P-ch transistor and a third power source; and a sixth P-ch transistor connected between the gate of the first P-ch transistor and the third power source, wherein differential input signals are applied to the gates of the first N-ch transistor and the second N-ch transistor, a bias voltage is applied to the gates of the third P-ch transistor and the fourth P-ch transistor, the gate of the fifth P-ch transistor is connected to a connection node of the first P-ch transistor and the first N-ch transistor, and the gate of the sixth P-ch transistor is connected to a connection node of the second P-ch transistor and the second N-ch transistor.