发明名称 |
NONVOLATILE MEMORY DEVICE |
摘要 |
A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit. |
申请公布号 |
US2017011799(A1) |
申请公布日期 |
2017.01.12 |
申请号 |
US201614996249 |
申请日期 |
2016.01.15 |
申请人 |
LEE JI-SANG;KWAK DONGHUN;BYEON DAESEOK;YOON CHIWEON |
发明人 |
LEE JI-SANG;KWAK DONGHUN;BYEON DAESEOK;YOON CHIWEON |
分类号 |
G11C16/10;G11C16/24;G11C16/04;G11C16/30;G11C16/08;G11C16/26 |
主分类号 |
G11C16/10 |
代理机构 |
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代理人 |
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主权项 |
1. A nonvolatile memory device comprising:
a memory cell array including a plurality of memory blocks each including a plurality of cell strings, each cell string including a ground selection transistor, a plurality of memory cells, and a string selection transistor; a row decoder circuit configured to apply a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device; and a page buffer circuit configured to apply, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and to apply the first voltage and a second voltage lower than the first voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data, wherein write data is loaded onto the page buffer circuit during the first precharge operation. |
地址 |
IKSAN-SI KR |