| 摘要 |
A division apparatus comprises circuitry storing an input data value; divider circuitry splitting the input value into sub-value(s) depending on a number of lanes for a current iteration, each sub-value occupying a lane; and to operate on each sub-value to generate a quotient corresponding to the division of that sub-value by a divisor, wherein the divisor is an odd integer; with remainder circuitry to operate on each sub-value to generate a remainder corresponding to the remainder of dividing the sub-value by the divisor; concatenation circuitry concatenates each quotient to produce a concatenated division value, and each remainder is concatenated to produce a concatenated remainder value. In subsequent iterations, the input data value is formed from a concatenated remainder value of a preceding iteration. Circuitry outputs, after a plurality of iterations, a result of adding the concatenated division values produced by said plurality of iterations. In each subsequent iteration, the number of lanes preferably decreases by a factor of 2. The divisor is preferably 3 or 5; and the plurality of iterations is of order log(N), where N corresponds to the number of bits in the input data value. |
