发明名称 N階乗デュアルデータレートクロックデータリカバリ
摘要 System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. Each symbol in a sequence of symbols received from a plurality of signal wires is received in an odd transmission interval or an even transmission interval. A first clock signal is generated from transitions in signaling state of the wires occurring between each odd transmission interval and a consecutive even transmission interval. A second clock signal is generated from transitions in signaling state of the plurality of wires occurring between each even transmission interval and a consecutive odd transmission interval. The first and second clock signals are used to capture symbols received in even and odd transmission intervals, respectively.
申请公布号 JP6059404(B2) 申请公布日期 2017.01.11
申请号 JP20160518120 申请日期 2014.10.01
申请人 クアルコム,インコーポレイテッド 发明人 仙石 祥一郎
分类号 H04L7/02;H04L25/02 主分类号 H04L7/02
代理机构 代理人
主权项
地址
您可能感兴趣的专利