发明名称 マルチコアプロセッサ、画像形成装置およびプログラム
摘要 PROBLEM TO BE SOLVED: To suppress occurrence of processing for switching a plurality of processor cores that are different in performance.SOLUTION: A processor core 101A and a processor core 101B include determination means 1011 (1011A and 1011B) and switching means 1012 (1012A and 1012B) as functional components. The determination means 1011 determines a threshold Th for the magnitude of load by which processing by the processor core 101A and processing by the processor core 101B are switched. The determination means 1011 determines the threshold Th according to at least one of the hardware configuration and software configuration of an image forming apparatus 1. The switching means 1012 switches between processing by the processor core 101A and processing by the processor core 101B according to the magnitude of the load applied to a processor 101 and the threshold Th determined by the determination means 1011.
申请公布号 JP6056683(B2) 申请公布日期 2017.01.11
申请号 JP20130138937 申请日期 2013.07.02
申请人 富士ゼロックス株式会社 发明人 三嶋 達央;佐藤 貞樹;根津 満尚;齊藤 真人;清水 健一郎;能條 英紀
分类号 G06F9/50 主分类号 G06F9/50
代理机构 代理人
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