发明名称 UNIVERSAL INPUT / OUTPUT CIRCUIT
摘要 The present disclosure is about a universal input / output circuit for building automation. The circuit of the present disclosure avoids issues due to capacitor soakage thereby giving more accurate measurements of electric resistance. To mitigate capacitor soakage, the voltage between the input/output terminals X0, M is held constant. A programmable source 25 drives a current through a resistor which connects to the input/output terminals. The circuit then measures a value of electrical resistance. The measurement yields a voltage signal which is transferred from the input of an analog-to-digital converter to the input of a digital-to-analog converter. A unity gain amplifier 15 applies the output voltage of the digital-to-analog converter D/A to the terminal X0. The circuit is configured such that the voltage signal at the output of the amplifier 15 matches or substantially matches the voltage obtained from the resistance measurement.
申请公布号 EP3115854(A1) 申请公布日期 2017.01.11
申请号 EP20150175814 申请日期 2015.07.08
申请人 Siemens Schweiz AG 发明人 Stoll, Walter
分类号 G05B19/042 主分类号 G05B19/042
代理机构 代理人
主权项
地址
您可能感兴趣的专利