发明名称 Semiconductor structure and manufacturing method of the same
摘要 Present disclosure provides a semiconductor structure, including a substrate having a center portion and an edge portion, an isolation layer over the substrate; a semiconductor fin with a top surface and a sidewall surface, partially positioning in the isolation layer, a first gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at an edge portion of the substrate, and a second gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at a center portion of the substrate. A lower width of the first gate in proximity to the isolation layer is smaller than an upper width of the first gate in proximity to top surface of the semiconductor fin.
申请公布号 US9543381(B2) 申请公布日期 2017.01.10
申请号 US201414483636 申请日期 2014.09.11
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. 发明人 Chen Chang-Yin;Cheng Tung-Wen;Chang Che-Cheng;Wu Po-Chi;Lin Jr-Jung;Lin Chih-Han
分类号 H01L27/088;H01L29/06;H01L29/66;H01L29/78;H01L29/165;H01L21/8234 主分类号 H01L27/088
代理机构 WPAT, P.C., Intellectual Property Attorneys 代理人 WPAT, P.C., Intellectual Property Attorneys ;King Anthony
主权项 1. A semiconductor structure, comprising: a substrate having a center portion and an edge portion; a plurality of semiconductor dies over the substrate, the edge portion including a region where at least one side of the semiconductor die being in contact with the circumference of the substrate; an isolation layer over the plurality of semiconductor dies; a semiconductor fin with a top surface and a sidewall surface, partially positioning in the isolation layer; a first gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at the edge portion of the substrate; and a second gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at the center portion of the substrate, wherein a lower width of the first gate in proximity to the isolation layer is smaller than an upper width of the first gate in proximity to top surface of the semiconductor fin.
地址 Hsinchu TW